TPU Simulator Release Notes for all builds of V3.4X

V3.40A New Features and Fixed Bugs

Bug 0: A call with no flush, to a subroutine that does the funny dec-repeat-no-flush-return thing, double-executes the non-flushed opcode following the return.

Overview: In the following code-snipped, the opcode immediatly following the call is executing twice. In this case the 'P' register equals '2' instead of '1'.

ram p<-#0;
call xy, flush.
au p:=p+1;          // THIS EXECUTES TWICE
ram p->(4,5).
...

xy:
au dec:=a.
ram diob<-by_diob;
return,no_flush.
repeat;
au diob:=R>diob,ccl.

Status: Fixed.

 Change 1: Openning the master behavior verification file from the menu is no longer supported.

Overview: In the files menu, the "Open master behavior Verfication, ... " no longer appears.

Discussion: Behavior verification files allow pin transitions to be verified. In order to support automation, this files should be explicitly loaded within a script command file, using the following script:

read_behavior_file("MasterGold.bv");

In previous versions the could be loaded from within the gui, and then later implicitly loaded from a project file. This implicit loaded was problematic and in order to avoid these problems it the implicit loading along with the accomanying menuing is no longer supported.

Status: Fixed.

Bug 1: Vector(); script command doesn't always work.

Overview: The vector("FileName.Vector"); command is unable to open the vector file in when the simulator is launched from a different working directory than the project file. This prevents automation from working in certain cases..

Discussion: The path to the vector file is now de-referenced relative to the project file.

Status: Fixed.

Bug 2: load_isr(); script command doesn't always work.

Overview: Same exact problem and solution as Bug 1.

Discussion: See bug 1.

Status: Fixed.

Bug 3: load_isr(); script command within an ISR script locks up the application.

Overview: A warning has been added to detect and alert the user. The load_isr(); script is now ignored such that the application does not lock up.

Status: Fixed.

Bug 4: In some cases ISR script files were getting executed when the should not be.

Overview: In order for a TPU channel'sISR script file to be exected there must be an interrupt that is both pending, and enabled. Instead, the ISR script file is executed regardless of whether the ISR is enabled or not (CIER).

Status: Fixed.

V3.41D New Features and Fixed Bugs

Bug 1: The BRANCH portion of the verify_coverage script commands were not working correctly.

Overview: When verifying branch coverage using a script command such as the following.

verify_file_coverage(...); verify_all_coverage(...);

The branches calculations are not being calculated correctly. Specifically, branch coverage should get 0% coverage if the branch has not been executed at all, and 100% if both branch paths (true & false) have been executed, and this is working correctly. The problem is with the 50% cases. If only the 'true" path has been taken than the coverage is supposed to be 50%. But instead it remains at 0%. And if only the "false" path has been taken that then coverage is also supposed to be 50%, but instead a value of 100% is used. Note that in the visual interface (the red/green/blue/white boxes) it works per the specification.

Status: Fixed.

 Bug 2: When setting CPR to zero while thread is executing disables channel.

Overview: Normally if the Channel Priority Register (CPR) is zero, the thread will not start executing. When the CPR is set to one, then a thread can execute (assuming there is a pending HSR, LINK, MRL or TDL event.) But if the CPR is set to zero for a channel that also happens to be executing when the CPR is set to zero, then the thread executes to completion ... which is good, this is the way it should and does work. But the problem is this. If a NEW HSR, LINK, MRL or TDL event occurs after the end of the thread, then is certain cases, the thread will not execute. The specific problem is that NEGATE SGL is ONLY called at the end of a thread. But since the CPR has been set to zero, then the SGL for that channel is never cleared. This fix is to perform an NEGATE SGL at times besides just the very end of a thread.

Status: Fixed.

Bug 3: Time slot transition trace always shows "index" as 0.

Overview: In the trace window data for time slot transitions is displayed. Index is supposed to be the entry table index for the thread, and as such should contain 0...15. But instead it always contains 0. Not only has this been fixed, but additional state information such as TDL, MRL values are now being displayed.

Status: Fixed.

Bug 4: HSR is being reset at beginning of thread.

Overview: A Host Service Request (HSR) can cause a channel to execute a thread. At the end of the thread, the HSR should get cleared, assuming the HSR was set at the beginning of the thread. This can be useful for host side for determining if a thread has completed. But the HSR was getting set at the beginnning of the thread instead of the end.

Status: Fixed.

V3.42B New Features and Fixed Bugs

Bug 1: The clear_worst_case_threads(); script command is not functional.

Overview: This script command is used for the channel window's worst-case thread display. It effectively allows the user to ignore the initialization threads which do not (generally) contribute to a channel's worst-case thread calcuation. This is handy for preventing those threads from interfering with the simulator's ability to display the effective worst case thread length.

Status: Fixed.

V3.42D and V3.42E New Features and Fixed Bugs

Bug 1: Errant internal simulator error message generated when fetching an invalid RAM location in TPU1.

Overview: For TPU1 ONLY if an invalid DATA RAM (PRAM) location is accessed (the un-implemented parameters 7 or 8 in channels 1 through 14) then a zero is loaded into memory. If the tracing is turned on of memory reads, then this results in an errant error message reporting an internal simulator error.

Status: Fixed.

Improvement 1: Added Additional Event Info to Trace Buffer.

Overview: Added a trace record called "Event." This records one of the four possible event types, "HSR", "LSR", "MATCH", and "TRANSITION". It replaces, and extends to the rest of the event types the record "MatchCapture" (MACA in the parseable trace file.) Note that previously only a "MATCH" event was generating a trace record, now TDL, LSR, and HSR are also generating trace records.

Overview: Negation of HSR, LSR, TDL and MRL events has been added to the trace buffer. Also, arming of match events has been added.

Overview: Added a trace record type called Event Arm. It is only for matches, and occurs when MRLE is set.

Overview: Added a trace record type called "Capture." This replaces the trace record previously called "MatchCapture" (see above.) This new "Capture" record type is only for captures, and no longer goofily records matches.

Improvement 2: Trace buffer order of TST, Entry Fetch, and Preload.

Overview: Intuitely, if seems like the Time Slot Transition occurs first, then the entry table address fetch, the read of a preload into P or DIOB. These records now are stored in the trace buffer in this order.

Improvement 3: Improved Logic Analyzer Window

Overview: In logic analyzer window, adding ability to drop a time into the waveform pane to perform a "GOTO TIME." Previously, a "time" had to be dropped into the itty-bitty "CurrentTime" field in order to perform this function.

Improvement 4: Removed Redundant Trace Lines

Overview: Removed redundant divider lines from the trace. This can significantly improve the simulation speed, especially when logging of TCR1 increments is disabled. See above for measured performance improvement. It also makes the trace easier to read because the eTPU is generally idle, and this was causing tons of divider lines to dominate the trace display.

Change 1: Trace File/Display Minor Formatting Changes

Overview: Made multiple cosmetic changes to the parse-able trace files such that the file is more consistent and therefore more testable.
   - VAL field changed to be upper case (0x1a2b --> 0x1A2B)
   - SRL, SGL, CTR, TCR1, TCR2, variable length instead of
      fixed length (0x000000A3 --> 0xA3)
   - NUMBITS, CHAN, FREERUN, THREAD, PRIORITY PINVAL
      changed to hexadecimal instead of integer (16 --> 0x10)
   - BAD changed from bool to hexadecimal (true --> 0x1, false --> 0x0)

Overview: Removed a goofey trace record called "MatchCapture." This record was part event (match) and part capture, and was therefore not really a distinct, singular record. It is split into two distinct records;"Event" and "Capture" ... see below.

Overview: Changed order in which records associated with a time slot transition are stored in the trace buffer. Intuitely, if seems like the Time Slot Transition occurs first, then the entry table address fetch, the read of a preload into P or DIOB. These records now are stored in the trace buffer in this order.