TPU Simulator Release Notes for all builds of V3.5X

V3.50D New Features and Fixed Bugs

Bug 1: [2007-April-21] The SRI (Match Transition Service Inhibit) bit not operating correctly relative to the entry point.

Overview: Consider the following sequence of events.

• A match occurs on a channel in which the SRI is asserted such that no thread occurs
• The channel receives a link.

The simulator was executed the thread corresponding to MRL/TDL==1 and LSR==1 whereas and this was wrong! Instead, the proper thread is MRL/TDL==0, LSR==1. SRI being asserted for that channel causes the thread that executes to correspond to the MRL being cleared.

Status: Fixed.